Arithmetic logic units (ALUs) having n-bits, where n is an integer, and which perform carry select addition are well known in the art. As discussed in Computer Arithmetic by Kai Hwang (John Wiley and Sons, 1979, pp. 81-84), a carry select adder utilizes predetermined ranked subdivisions of two numbers which are to be added. Two sums for each of the predetermined subdivisions are typically generated by two parallel adder circuits. One sum corresponds to a sum having a carry-in bit of zero, and the other sum corresponds to a sum having a carry-in bit of one. The two sums of each subdivision are coupled to a multiplexer which couples a predetermined one of the sums to an output in response to a carry-in bit. Carry-out bits are generated for each sum and are coupled to logic means associated with each of the ranked subdivisions except the first subdivision. The logic means control the multiplexer of each subdivision and determine which of the two sums associated with each subdivision is coupled to an output. In carry select addition, carry propagation is reduced to a smaller bit ripple carry. Disadvantages however include the fact that two parallel adders exist for each of the predetermined subdivisions. The logic means associated with the ranked subdivisions greater than lowest rank also noticeably increase the physical size of the carry select adder circuit.